The present invention relates to a temperature sensor capable of determining temperatures on a semiconductor chip with satisfactory accuracy without depending on a variation in source potential, variations in manufacturing process and the like.
As techniques each related to a temperature sensor, there have heretofore been known ones described in, for example, a document patent 1 (Japanese Unexamined Patent Publication No. Hei 5(1993)-306958) and a non-document patent 1 (Symp VLSI Circuits Dig 7 “5-2 Low Power Self Refresh Mode DRAM With Temperature Detecting Circuit” Memory Division, Matsushita Electronics Corp. Nagaokakyo 617, Japan, 1993-5, P. 43-44).
A technique for a temperature detection circuit capable of performing temperature detection independent on a manufacturing process, using a bandgap circuit has been described in the patent document 1.
A technique for a temperature sensor mounted to a dynamic random access memory (hereinafter called “DRAM”) has been described in the non-patent document 1.
In order to reduce a self-refresh current in the DRAM, for example, each temperature in a semiconductor chip is detected by the temperature sensor, and a refresh frequency is lowered at a low temperature and raised at a high temperature.
FIG. 6 is a block diagram showing a temperature sensor equipped with the conventional DRAM described in the non-patent document 1.
The DRAM shown in FIG. 6 has different types of devices (for example, a temperature sensor 10-1 for 70° C., a temperature sensor 10-2 for 45° C. and a temperature sensor 10-3 for 15° C.) different in temperature characteristic, for detecting temperatures in a semiconductor chip. A refresh timer selection circuit 20 is connected to output terminals of these devices. The refresh timer selection circuit 20 is a circuit that selects time-measuring timers 21 through 24 corresponding to the respective temperature sensors 10-1 through 10-3, based on temperature detection results of the temperature sensors 10-1 through 10-3. The timer 21 is a timer short in measurement time when a semiconductor chip temperature Ta is higher than 70° C. (Ta>70° C.). The timer 22 is a timer rather short in measurement time when 70° C.>Ta>45° C. The timer 23 is a timer rather long in measurement time when 45° C.>Ta>15° C. The timer 24 is a timer long in measurement time when Ta<15° C. Any one of the timers 21 through 24 is selected by the refresh timer selection circuit 20. A refresh operation of each DRAM memory cell is performed by a self-refresh controller 25 at measurement time intervals of the selected timer.
Since the time taken up to the disappearance of an electric charge stored in the DRAM memory cell is short when the temperature in the semiconductor chip is high, a refresh time interval is set short (i.e., a refresh frequency is raised). Since the time taken up to the disappearance of the electric charge is long when the temperature is low, the refresh time interval is set long (i.e., the refresh frequency is lowered) and a self-refresh current is hence reduced.
The temperature sensor 10-1 for 70° C. comprises an N well resistor 11-1 and polysilicon resistors 11-2 through 11-4 lying in a semiconductor substrate, temperature sensor activating N channel type MOS transistors (hereinafter called “NMOSs”) 12-1 and 12-2 on/off-operated by a control signal DTC, a P-type sense amplifier 13 constituted of P channel type MOS transistors (hereinafter called “PMOSs”) 13-1 and 13-2 that amplify a difference in potential between a node A placed between the N well resistor 11-1 and the polysilicon resistor 11-2 and a node B located between the polysilicon resistors 11-3 and 11-4, an N-type sense amplifier 14 constituted of NMOSs 14-1 and 14-2 that amplify the potential difference between the nodes A and B, P-type sense amplifier activating PMOSs 15-1 and 15-2 on/off-operated by a control signal SEP, and N-type sense amplifier activating NMOSs 16-1 and 16-2 on/off-operated by a control signal SEN.
Other temperature sensors 10-2 and 10-3 for 45° C. and 15° C. are also simply different in temperature vs. voltage characteristic and respectively configured by a similar circuit.
FIG. 7 is a diagram showing a timing chart for describing the control signals shown in FIG. 6. The horizontal axis indicates the time and the vertical axis indicates a logical level (“H” or “L” level). FIG. 8 is a potential relational diagram of temperature vs. nodes A and B, which is indicative of potential states based on temperature transitions at the nodes A and B. The horizontal axis indicates the temperature [° C.] and the vertical axis indicates the voltage [V].
The operation of the temperature sensor 10-1 will be described for instance. When the control signal DTC is brought to an “H” level, the NMOSs 12-1 and 12-2 are respectively brought to an on state, so that source currents flow through the resistors 11-1 and 11-2 and the resistors 11-3 and 11-4 respectively series-connected between the source potential VDD and ground GND. Next, the control signal SEN is brought to an “H” level so that the NMOSs 16-1 and 16-2 are respectively placed in an on state, thereby activating the N-type sense amplifier 14. Subsequently, the control signal SEP is brought to an “L” level so that the PMOSs 15-1 and 15-2 are respectively placed in an on state to activate the P-type sense amplifier 13. In doing so, a difference in potential occurs between the nodes A and B due to the voltage division of the resistors 11-1 through 11-4 different in temperature vs. resistance value. This is amplified by the sense amplifiers 13 and 14, after which a detection voltage corresponding to a detected temperature is outputted and sent to the refresh timer selection circuit 20. Other temperature sensors 10-2 and 10-3 are also operated in like manner and detection voltages corresponding to detected temperatures are outputted and sent to the refresh timer selection circuit 20.
The refresh timer selection circuit 20 compares detection voltages sent from the temperature sensors 10-1 through 10-3 and logically determines whether the temperature chip temperature Ta belongs to a temperature range of any of Ta>70° C., 70° C.>Ta>45° C., 45° C.>Ta>15° C. and Ta<15° C., thereby selecting the corresponding one timer (one of the timers 21 through 24). On the basis of the above result of selection, a refresh operation relative to each DRAM memory cell is performed at set time intervals of the selected timer under the control of the cell refresh controller 25.
The conventional circuit such as shown in FIG. 6, however, determines the semiconductor chip temperature Ta from the potential states based on the temperature transitions of the nodes A and B, which are generated due to a temperature gradient difference between the plural temperature sensors 10-1 through 10-3 corresponding to the different types of devices different in temperature characteristic. Therefore, the design of margins is difficult when the cumbersomeness for fabrication of the plural temperature sensors 10-1 through 10-3 and variations in characteristic are taken into consideration. It was thus difficult to reduce variations in manufacturing process and enhance the accuracy of temperature decisions.